In contrast to traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETs), which are fabricated using conventional lithographic fabrication methods, nonplanar FETs incorporate various vertical transistor structures. One such semiconductor structure is the “FinFET,” which takes its name from the multiple thin silicon “fins” that are used to form the respective gate channels, and which are typically on the order of tens of nanometers in width.
More particularly, referring to the exemplary prior art nonplanar FET structure shown in FIG. 1, a FinFET 100 generally includes two or more parallel silicon fin structures (or simply “fins”) 104 and 106. These structures are typically formed using a silicon-on-insulator (SOI) substrate (not shown), with fins 104 and 106 extending between a common drain electrode and a common source electrode (not shown). A conductive gate structure 102 “wraps around” three sides of both fins 104 and 106, and is separated from the fins by a standard gate oxide layer 103. While FIG. 1 illustrates only one gate structure 102 wrapped around fins 104 and 106, two or more parallel gate structures can be wrapped around the fins.
Fins 104 and 106 may be suitably doped to produce source/drain regions, as is known in the art, such that a gate channel is formed within the near surface of the fins adjacent to gate oxide 103. Sidewall spacers typically are formed about the sidewalls of the gate structures for distancing the source/drain regions from the channel, as in planar FET formation. However, unlike typical planar FET formation, during FinFET formation, the sidewall spacer-forming material must be etched away from the vertical sidewalls of the fins. The vertical sidewalls of the fins are the equivalent of the source/drain regions of planar FETs and must be exposed so that source/drain junctions can be formed.
To remove the sidewall spacer-forming material from the fins, the etching of the sidewall spacer-forming material must continue past the normal end point of the etch, that is, an overetch must be performed, until the entire thickness of the spacers on the fin sidewalls has been etched away. However, this overetch can cause several difficulties. For example, to prevent the sidewall spacers from being etched from the sidewalls of the gate structures, the gate structures must be made tall relative to the fins so that the spacers about the gate structures have sufficient width to withstand the overetch. The taller the gate structures, however, the greater the capacitance between the gate structure and the source/drain regions. In addition, hard mask material can be removed from the gate structures during the overetch. The semiconductor substrate upon which the gate structures and fins are disposed also is exposed to the overetch, leading to undercutting of the fins and weakening of their mechanical support. Moreover, the sidewalls of the fins are exposed to the overetching, leading to roughening of and damage to the source/drain areas on the sidewalls of the fins.
Accordingly, it is desirable to provide methods for forming semiconductor structures using selectively-formed sidewalls spacers. In addition, it is desirable to provide methods for forming FinFET structures having spacers formed about gate structures of the FinFET structures but not the fins. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.